1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices and in particular to a semiconductor integrated circuit device operating synchronously with an external clock signal. More specifically, the present invention relates to e.g. a synchronous semiconductor memory device operating synchronously with an external clock signal.
2. Description of the Background Art
With the recent improvement in the operating speed of microprocessors (MPUs), synchronous DRAM (SD and the like operating synchronously with a clock signal have been used to achieve rapid access to dynamic random access memory (DRAM) and the like used as a main memory device.
The operating speed of recent semiconductor integrated circuit devices other than the SDRAM described above have also been significantly improved with the improvement of the microfabrication technology, designing technology and the like therefor.
During the process for manufacturing semiconductor integrated circuit devices such as DRAMs or prior to shipping the products, a so-called tester device is used to estimate the electrical characteristics of the products to determine whether the products are defective and ensure their reliability.
However, the improvement in the operating speed of the SDRAM and the like described above also requires the operating speed of the tester device to be improved to correspond to the operating speed of the device to be tested and this tends to increase the testing cost.
3. Description of the Background Art
FIG. 21 is a schematic block diagram showing an entire configuration of a conventional SDRAM 2000 having a capacity of 1 G bit.
SDRAM 2000 includes: an internal control clock generation circuit 8 receiving an external clock signal ext.CLK via a clock input terminal 2 and a clock input buffer 4 and outputting an internal clock signal int.CLK; a mode decoder 22 receiving via input buffers 12 to 20 the control signals supplied via an external control signal input terminal 10 to output internal control signals; an input terminal 22 receiving a reference potential Vref for determining whether an input signal is of high level or low level; a mode register 46 responsive to an address signal supplied via an address signal input terminal 30 and to a control signal for setting and holding the information for an operation mode of SDRAM 2000, such as data on burst length; and a row address buffer/column address buffer 32-38 receiving address signals A0 to A12 supplied via address signal input terminal 30 and controlled by mode decoder 22 to respectively receive a row address and a column address supplied in time division manner.
SDRAM 2000 also includes: a self-refresh timer 54 controlled by mode decoder 22 to output a clock controlling a self-refresh operation while a self-refresh mode is set; a refresh address counter 56 controlled by self-refresh timer 54 to output an address signal provided during a self-refresh period; a multiplexer 58 receiving an output from refresh address counter 56 and an output from row address buffer 32-38 and selectively outputting the output from row address buffer 32-38 during a normal operation and the output from refresh address counter 56 during the period of the self-refresh mode; a bank address buffer 51 receiving bank addresses BA0 to BA2 supplied via address signal input terminal 30; a bank decoder receiving an output from bank address buffer 51 and outputting a designated bank address; a row predecoder 62 predecoding a row address in a designated bank; a burst address counter 60 receiving an output from column address buffer 51 and outputting a burst address depending on a set burst length while a burst mode is designated; and a column predecoder 64 receiving an output from burst address counter 60 and predecoding a column address in a selected bank.
SDRAM 2000 also includes: memory array blocks 100, 110, . . . , 120 respectively corresponding to banks 0 to 7; row decoders 102, 112, . . . , 122 respectively provided for the memory array blocks or banks, responsive to an output from bank decoder 66 and an output from row predecoder 62 for selecting a row in their respective banks; column decoders 104, 114, . . . , 124 provided for their respective banks, receiving an output from column predecoder 64 to select a column in their respective banks; input/output circuits 106, 116, . . . , 126 provided for their respective banks, supplying read data to a global I/O bus G-I/O and supplying written data from global I/O bus G-I/O to their respective memory array blocks; a read/write register 84 holding written data supplied to the global I/O bus and read data transferred from the global I/O bus; and a data input/output terminal 70 provided for read/write register 84 via bidirectional input/output buffers 72 to 82 for externally transmitting and receiving input/output data DQ0 to DQ31.
FIG. 22 are timing charts for representing an operation of the conventional SDRAM 2000 shown in FIG. 21.
It is assumed that at time t0 (not shown) when external clock signal ext.CLK rises, signals /CS and /RAS that each attain an active low level and an activated bank address that is designated activates the operation of the corresponding bank.
Furthermore, in response to an address signal supplied at time t0 an operation is effected to select the corresponding row.
Then, at time t1 when external clock signal ext.CLK rises, a write operation is designated in response to signals /CS, /CAS and /WE of active low level. In response to an address signal supplied at time t1, data are successively written (or a burst write operation is effected). More specifically, a signal WRITE indicative of the write operation in SDRAM 2000 attains an active high level and burst address counter 60 also outputs an internal address int.ADD depending on the designated burst length.
Responsively the written data supplied at a data input/output terminal DK at time T1 is latched by write register 84 provided in SDRAM 2000 and is transmitted to a selected memory array block via a global I/O bus D/I/O. The written data, transmitted via an I/O line pair M-I/O in the memory array block, is transmitted to a bit line pair BL in response to that column select signal YS corresponding to a memory cell column selected in response to internal address signal int.Add which is activated synchronously with a write clock signal WCLK generated in SDRAM 2000.
Responsively, the data is written in a selected memory cell.
Thereafter, the data supplied to data input/output terminal DK successively at times t2, t3 and t4 are similarly written in memory cells successively selected.
For a read operation, signals /CS and /RAS that are activated at time t6 (not shown) when external clock signal ext.CLK rises, activate a bank selected in response to a bank address signal.
Then at time t7 when external clock signal ext.CLK rises, the read operation is designated in response to signals /CS and /CAS of active low level, and in response to an address signal supplied at time t7 an operation is effected for selecting the corresponding column. In response to the address signal supplied at time t7, burst address counter 60 successively outputs burst addresses for a designated burst length of e.g. four.
In SDRAM 2000, in response to a read clock signal RCLK described a corresponding memory cell is selected and the data read is read via I/O line pair M-I/O and global I/O bus G-I/O and held in read write register 84. The read data corresponding to a column address supplied at time t7 is output to data input/output terminal DQ at time t9.
Thereafter, similarly the data read from the burst addresses designated by burst address counter 60 are supplied to data input/output terminal DQ at times t10, t11 and t12 successively.
With the write and read operations of conventional SDRAMs effected as described above, increasing the frequency for effecting a test operation of SDRAM 2000 requires increasing an external clock frequency generated at the tester. This not only complicates the configuration of the tester but requires an expensive tester device.
In other words, there has been a disadvantage that the testing cost is increased in the process for manufacturing SDRAM 2000.
An object of the present invention is to provide a synchronous semiconductor integrated circuit device capable of reducing a testing cost associated with improvement in the operating speed of a device to be tested.
To sum up, the present invention is a synchronous semiconductor integrated circuit device operating in response to an external clock signal, externally receiving a control signal and externally transmitting and receiving data, the synchronous semiconductor integrated circuit device including an internal synchronization signal generation circuit, an internal circuit and a data input/output circuit.
The internal synchronization signal generation circuit is controlled by the control signal to generate in a first operation mode an internal clock signal corresponding to the external clock signal and in a second operation mode an internal clock signal activated in synchronization with activation of the external clock and also attaining an active state N times during one cycle of the external clock, wherein N is a natural number and larger than two.
The internal circuit is controlled by the control signal and synchronized with the internal clock signal to apply a predetermined process to the external data.
The data input/output circuit is synchronized with the internal clock signal to output the data from the internal circuit.
Therefore a main advantage of the present invention is that since the internal circuit in the second operation mode operates in synchronization with an internal clock signal which attains an active state N times during one cycle period of the external clock signal, a test operation provided in the second operation mode allows reduction of testing time and hence testing cost.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.